Physical Design Engineer — ASIC & RTL to GDSII

InvestedintheMission; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to join the Starlink ASIC team. You will perform partition synthesis, floorplanning, power/ground grid generation, place and route, and signoff checks to enable robust space-grade chips powering global connectivity.

Eligible candidates hold a bachelor's in EE/CE/CS with 1+ years in RTL2GDSII physical design and have experience with industry EDA tools, CMOS submicron physics, and scripting (Python, TCL, Bash).

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional RTL2GDSII physical design experience.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
• Develop/improve physical design methodologies and automation scripts for various implementation steps.
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Skills

RTL2GDSII

Physical design

EDA tools

Scripting

Collaboration

Education

Bachelor’s degree in electrical engineering, computer engineering or computer science

Tools

Python

TCL

Bash

Perl

Job description

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to join the Starlink ASIC team. You will perform partition synthesis, floorplanning, power/ground grid generation, place and route, and signoff checks to enable robust space-grade chips powering global connectivity.

Eligible candidates hold a bachelor's in EE/CE/CS with 1+ years in RTL2GDSII physical design and have experience with industry EDA tools, CMOS submicron physics, and scripting (Python, TCL, Bash).