Senior ASIC Physical Design Engineer — Space/Satcom

United States Digital Space LLC; Austin (CA); On-site; USD 175,000 - 280,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Medical, vision, dental insurance

401(k) retirement plan

Paid vacation and holidays

Job summary

United States Digital Space LLC is seeking a Sr. SoC/ASIC Physical Design Engineer to drive cutting-edge silicon for Starlink deployments. You will join a cross-disciplinary team and contribute to partitioning, synthesis, floorplanning, place-and-route, timing, and signoff.

Ideal candidates have extensive experience with RTL-to-GDSII flows, EDA tools, and deep sub-micron physics, with a focus on reliability and performance in space-ground infrastructure applications.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 5+ years of ASIC and/or physical design flow development experience.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Skills

ASIC design

RTL2GDSII

signoff flows

scripting

collaboration

DFT/MBIST/LBIST

Education

Bachelor’s degree in EE/CE/CS

Tools

EDA tools

Job description

United States Digital Space LLC is seeking a Sr. SoC/ASIC Physical Design Engineer to drive cutting-edge silicon for Starlink deployments. You will join a cross-disciplinary team and contribute to partitioning, synthesis, floorplanning, place-and-route, timing, and signoff.

Ideal candidates have extensive experience with RTL-to-GDSII flows, EDA tools, and deep sub-micron physics, with a focus on reliability and performance in space-ground infrastructure applications.