Silicon Physical Design Engineer (RTL to GDSII)

SPACE EXPLORATION TECHNOLOGIES CORP; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Long-term incentives

Stock or long-term cash awards

Discretionary bonuses

Employee Stock Purchase Plan

Medical, vision, dental

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) for Irvine, CA. You will work on cutting-edge ASICs for Starlink, collaborating with cross-disciplinary teams to deliver robust physical design solutions.

The role emphasizes partition synthesis, floorplanning, timing, power, area targets, and signoff. Strong scripting and EDA tool familiarity are required, with optional advanced design skills and weekend availability.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
• Develop/improve physical design methodologies and automation scripts for various implementation steps.
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Skills

RTL2GDSII

Scripting (Python, TCL, Bash)

Team collaboration

Education

Bachelor's degree in electrical engineering, computer engineering or computer science

Tools

EDA tools

Job description

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) for Irvine, CA. You will work on cutting-edge ASICs for Starlink, collaborating with cross-disciplinary teams to deliver robust physical design solutions.

The role emphasizes partition synthesis, floorplanning, timing, power, area targets, and signoff. Strong scripting and EDA tool familiarity are required, with optional advanced design skills and weekend availability.