Physical Design Engineer II — Space ASICs for Starlink

United States Digital Space LLC; Austin (CA); On-site; USD 145,000 - 195,000; Full time

Job summary

United States Digital Space LLC is seeking a Physical Design Engineer II (Silicon Engineering) to develop next-generation ASICs for Starlink deployments. The role involves partition synthesis, physical design, and close collaboration with cross-disciplinary teams to push performance and reliability for space and ground systems.

Qualifications include a Bachelor’s in ECE/CS and 3+ years in RTL2GDSII or physical design flow, plus experience with EDA tools and scripting.

Qualifications

• Bachelor’s degree required in electrical engineering, computer engineering or computer science.
• 3+ years of professional RTL2GDSII physical design experience or flow development.

Responsibilities

• Perform partition synthesis and physical implementation steps (synthesis, floorplanning, P/G grid, place & route, timing, noise, physical verification, electromigration, voltage drop, signoff checks).
• Develop/improve physical design methodologies and automation scripts for implementation steps.
• Collaborate with ASIC design team to drive feasibility studies, targets, and RTL/design tradeoffs.
• Resolve design/timing/congestion and flow issues and drive execution.
• Run, debug, and fix signoff closure issues in STA, noise, EC, PD verifications.

Skills

RTL2GDSII flow

EDA tools knowledge

Scripting: Python/Perl/TCL

Problem solving

Team collaboration

Education

Bachelor’s degree in electrical/computer engineering or computer science

Tools

Standard CMOS design tools

DFT/Scan/MBIST/LBIST basics

Job description

United States Digital Space LLC is seeking a Physical Design Engineer II (Silicon Engineering) to develop next-generation ASICs for Starlink deployments. The role involves partition synthesis, physical design, and close collaboration with cross-disciplinary teams to push performance and reliability for space and ground systems.

Qualifications include a Bachelor’s in ECE/CS and 3+ years in RTL2GDSII or physical design flow, plus experience with EDA tools and scripting.