Onsite Senior Physical Design Engineer for AI ASIC

Acceler8 Talent; California; On-site; USD 150,000 - 210,000; Full time

Job summary

Acceler8 Talent is seeking a seasoned Physical Design Engineer to drive the backend implementation of a next‑generation AI accelerator. You will own floorplanning, placement, timing closure, power optimization, and tapeout readiness for a high‑performance ASIC.

You will collaborate with RTL, architecture, and implementation teams to ensure designs meet physical constraints and performance targets while staying hands‑on in debugging and issue resolution.

Qualifications

• Substantial hands-on experience in digital ASIC physical design and backend implementation.
• Ownership of physical implementation work on complex ASIC/SoC designs.
• Strong ability to analyze and optimize PPA trade-offs and constraints.

Responsibilities

• Contribute to floorplanning and physical implementation of complex digital ASIC designs.
• Analyze and optimize power, performance, and area trade-offs during implementation.
• Identify constraints requiring RTL or architectural changes.
• Investigate and resolve issues in floorplanning, timing, power, and design closure.
• Collaborate with RTL and microarchitecture teams to align frontend and backend goals.
• Coordinate with internal teams and external partners for design handoffs.
• Support physical verification, implementation sign-off, and tapeout readiness.
• Track issues and drive engineering solutions to closure.

Skills

Digital ASIC physical design

Floorplanning

Placement

Timing constraints

Power optimization

Physical verification

RTL/microarchitecture collaboration

Debugging physical issues

Tools

STA

Job description

Acceler8 Talent is seeking a seasoned Physical Design Engineer to drive the backend implementation of a next‑generation AI accelerator. You will own floorplanning, placement, timing closure, power optimization, and tapeout readiness for a high‑performance ASIC.

You will collaborate with RTL, architecture, and implementation teams to ensure designs meet physical constraints and performance targets while staying hands‑on in debugging and issue resolution.