Senior ASIC Power Architect for AI Inference (Remote)

Positron; United States; À distance; USD 200 000 - 300 000; Plein temps

Avantages offerts par ce poste

Medical/Dental/Vision

Life Insurance

Unlimited PTO

Remote-first culture

401(k)

Résumé du poste

Positron AI is seeking a Senior ASIC Physical Design Engineer - Power to lead power estimation, modeling, and optimization across critical blocks for our AI accelerator roadmap. You will collaborate with Architecture, RTL, and Backend teams to push power efficiency and performance per watt.

This role emphasizes UPF/CPF, power integrity, and cross-functional validation, with mentorship for junior engineers and a scalable power methodology for future chips.

Qualifications

• 8+ years of ASIC design or implementation experience with a focus on power.
• Hands-on UPF/CPF power specification and verification flows.
• Strong proficiency with PrimePower and Joules or equivalent power analysis tools.
• Experience working with advanced process nodes.
• A solid grasp of RTL design and its impact on chip power.
• Track record of contributing to power targets on production silicon.
• Strong Tcl and/or Python scripting for analysis and automation.

Responsabilités

• Own power approaches for assigned blocks and subsystems across dynamic power, leakage, clock, memory, interconnect and peak power.
• Build and maintain accurate power models across the development lifecycle.
• Implement and drive power optimization techniques including clock gating, power gating, and DVFS.
• Work with backend on IR drop, EM, power distribution and UPF specifications.
• Collaborate with Architecture, RTL, Backend, Firmware, Thermal, Packaging and System Engineering teams.
• Leverage AI-driven tools to improve power analysis, regression triage and anomaly detection.

Connaissances

UPF/CPF

Power analysis tools

RTL design impact

Tcl/Python scripting

Process nodes experience

Outils

PrimePower

Joules

UPF/CPF verification

Description du poste

Positron AI is seeking a Senior ASIC Physical Design Engineer - Power to lead power estimation, modeling, and optimization across critical blocks for our AI accelerator roadmap. You will collaborate with Architecture, RTL, and Backend teams to push power efficiency and performance per watt.

This role emphasizes UPF/CPF, power integrity, and cross-functional validation, with mentorship for junior engineers and a scalable power methodology for future chips.