New Grad Design Verification Engineer - AI Chip RTL

SambaNova, Inc.; San Jose (CA); Vor Ort; USD 120.000 - 150.000; Vollzeit

Benefits dieser Stelle

Health insurance

Equity

Well-being benefits

Zusammenfassung

SambaNova is hiring a new graduate Design Verification Engineer in San Jose, CA to write testbenches, tests, checkers, and coverage for the RDU chip using SystemVerilog and UVM. You will run regressions, debug simulation failures, and partner with RTL designers to fix bugs before tape-out.

Required: BS in Electrical/Computer Engineering or Computer Science, coursework in digital design and computer architecture, experience with SystemVerilog/Verilog, UVM, and scripting (Python, Perl, TCL or

Qualifikationen

• BS in Electrical Engineering, Computer Engineering, or Computer Science.
• Coursework or project experience in digital design and computer architecture
• Experience with SystemVerilog or Verilog
• Scripting experience in Python, Perl, TCL, or shell
• Experience with UVM
• Familiarity with constrained‑random verification, functional coverage, and assertions
• Familiarity with clock domain crossing concepts

Aufgaben

• Write and execute verification plans for chip‑level control and initialization features
• Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage
• Write directed and constrained‑random tests to find corner cases
• Debug simulation and regression failures with RTL designers
• Analyze functional and code coverage and close coverage gaps

Kenntnisse

SystemVerilog

UVM

Python

Verilog

Digital design

Computer architecture

Clock domain crossing

Ausbildung

BS in EE/CE/CS

MS in EE/CE/CS

Tools

UVM

Jobbeschreibung

SambaNova is hiring a new graduate Design Verification Engineer in San Jose, CA to write testbenches, tests, checkers, and coverage for the RDU chip using SystemVerilog and UVM. You will run regressions, debug simulation failures, and partner with RTL designers to fix bugs before tape-out.

Required: BS in Electrical/Computer Engineering or Computer Science, coursework in digital design and computer architecture, experience with SystemVerilog/Verilog, UVM, and scripting (Python, Perl, TCL or