Design Verification Engineer – Digital RTL & UVM

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

Long‑term incentives

Employee Stock Purchase Plan

Health, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Job summary

SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.

The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a

Qualifications

• Bachelor's degree in electrical engineering, computer science or computer engineering.
• 1+ years of experience with design verification and test bench development.

Responsibilities

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non‑UVM) for testing designs, including DSP blocks
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs
• Contribute towards pre‑silicon verification, chip bring‑up and post‑silicon validation
• Be a hands‑on self‑starter who can execute the steps required to fully verify a complex digital designs

Skills

SystemVerilog

UVM

Python

MATLAB

Testbench development

ASIC verification

Education

Bachelor's degree in electrical engineering, computer science or computer engineering

Job description

SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.

The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a