ASIC Verification Engineer - New Grad (AI-Driven SoC)

NVIDIA Corporation

Santa Clara (CA)

Vor Ort

USD 100.000 - 190.000

Vollzeit

Vor 8 Tagen

Eine vollständige Bewerbung in einer Minute

Maßgeschneiderter Lebenslauf und Anschreiben – versandbereit.

Schaffe es an den ATS-Filtern vorbei

Benefits dieser Stelle

Equity
Benefits

Zusammenfassung

NVIDIA Corporation in Santa Clara, CA is hiring an ASIC Verification Engineer - New College Grad 2027 to contribute to pre-silicon verification and ensure hardware functionality. You’ll simulate the RTL under varied conditions to flush out design bugs early and help extend cutting-edge UVM testbench environments.

Qualifications include a BS, MS, or PhD in EE/CE or related field, coursework or internship in architecture or HDL (Verilog/VHDL), and strong programming in C++ or SystemVerilog.

Qualifikationen

  • BS/MS/PhD in EE/CE or related field is required or equivalent experience.
  • Coursework or internship exposure to computer architecture, logic design, and HDL languages (Verilog, VHDL).
  • Strong programming experience in C++ or SystemVerilog and understanding of OOP concepts.

Aufgaben

  • Contribute to complex UVM testbench environments including test development, automation, or analysis.
  • Develop directed or random tests in SystemVerilog to verify the reference C++ and RTL models in a simulation environment.
  • Debug RTL simulation failures and analyze results.
  • Collaborate across teams to implement AI-driven verification flows.

Kenntnisse

C++
SystemVerilog
UVM
Verilog
VHDL

Ausbildung

BS/MS/PhD in EE/CE

Tools

Verilator
ModelSim

Jobbeschreibung

NVIDIA Corporation in Santa Clara, CA is hiring an ASIC Verification Engineer - New College Grad 2027 to contribute to pre-silicon verification and ensure hardware functionality. You’ll simulate the RTL under varied conditions to flush out design bugs early and help extend cutting-edge UVM testbench environments.

Qualifications include a BS, MS, or PhD in EE/CE or related field, coursework or internship in architecture or HDL (Verilog/VHDL), and strong programming in C++ or SystemVerilog.

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