Design Verification Engineer, New Grad

SambaNova, Inc.; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Benefits offered by this job

Health insurance

Equity

Well-being benefits

Job summary

SambaNova is hiring a new graduate Design Verification Engineer in San Jose, CA to write testbenches, tests, checkers, and coverage for the RDU chip using SystemVerilog and UVM. You will run regressions, debug simulation failures, and partner with RTL designers to fix bugs before tape-out.

Required: BS in Electrical/Computer Engineering or Computer Science, coursework in digital design and computer architecture, experience with SystemVerilog/Verilog, UVM, and scripting (Python, Perl, TCL or

Qualifications

• BS in Electrical Engineering, Computer Engineering, or Computer Science.
• Coursework or project experience in digital design and computer architecture
• Experience with SystemVerilog or Verilog
• Scripting experience in Python, Perl, TCL, or shell
• Experience with UVM
• Familiarity with constrained‑random verification, functional coverage, and assertions
• Familiarity with clock domain crossing concepts

Responsibilities

• Write and execute verification plans for chip‑level control and initialization features
• Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage
• Write directed and constrained‑random tests to find corner cases
• Debug simulation and regression failures with RTL designers
• Analyze functional and code coverage and close coverage gaps

Skills

SystemVerilog

UVM

Python

Verilog

Digital design

Computer architecture

Clock domain crossing

Education

BS in EE/CE/CS

MS in EE/CE/CS

Tools

UVM

Job description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the‑art models with better performance, greater energy efficiency, and faster time to value.

About The Team

The Design Verification team verifies the RDU, SambaNova's chip for AI workloads. We build SystemVerilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and work with architects, RTL designers, and firmware engineers.

About The Role

As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out.

Responsibilities

• Write and execute verification plans for chip‑level control and initialization features
• Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage
• Write directed and constrained‑random tests to find corner cases
• Debug simulation and regression failures with RTL designers
• Analyze functional and code coverage and close coverage gaps

Required Qualifications

• B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Coursework or project experience in digital design and computer architecture
• Experience with SystemVerilog or Verilog
• Scripting experience in Python, Perl, TCL, or shell
• Experience with UVM
• Familiarity with constrained‑random verification, functional coverage, and assertions
• Familiarity with clock domain crossing concepts

Preferred Qualifications

• M.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Experience using AI tools such as Claude for verification development and debug
• Internship experience in design verification

Base Salary Range

Base Pay Range

$120,000-$150,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary For US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well‑being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.