Digital Verification Engineer — On-Site with Relocation Help

Snowcap Compute Inc.; San Francisco (CA); On-site; USD 140,000 - 230,000; Full time

Benefits offered by this job

Full medical, dental, and vision

401(k)

Relocation assistance

Job summary

Snowcap Compute Inc. seeks a senior verification engineer to own UVM testbench development for RTL blocks and full-chip netlists. You will drive functional coverage, write directed and constrained-random tests, and maintain the regression infrastructure.

You will work with the Digital Architect, Microarchitect, and RTL designers in a flat team, ensuring coverage closes and regressions stay green. On-site location options include SF Bay Area or Jacksonville, FL.

Qualifications

• Strong UVM and SystemVerilog verification methodology on production silicon.
• Track record of coverage-driven verification and closing coverage holes.
• Experience with formal verification tools and model checking.
• Solid knowledge of full chip design flow: RTL, synthesis, STA, back-end.
• Excellent debugging instincts and root-cause discipline.
• Scripting proficiency in Python or Perl for automation.

Responsibilities

• Own UVM testbench development for RTL blocks and full-chip netlist.
• Define functional coverage goals against microarchitecture specs and close holes.
• Write directed and constrained-random tests for SFQ-like logic behaviors.
• Build and own chip-level simulation environment and nightly regression.
• Drive debug cycles with RTL engineers and produce actionable artifacts.
• File, track, and triage functional bugs through to closure.
• Apply formal verification where it adds value, and know when to use it.
• Set verification standards, testbench architecture, and regression hygiene.

Skills

UVM testbench

SystemVerilog

Coverage-driven verification

Formal verification

Debugging

Python scripting

Perl scripting

Full-chip verification

Tools

Python

Perl

Simulation toolchain

Job description

Snowcap Compute Inc. seeks a senior verification engineer to own UVM testbench development for RTL blocks and full-chip netlists. You will drive functional coverage, write directed and constrained-random tests, and maintain the regression infrastructure.

You will work with the Digital Architect, Microarchitect, and RTL designers in a flat team, ensuring coverage closes and regressions stay green. On-site location options include SF Bay Area or Jacksonville, FL.