ML Accelerators RTL Engineer - ASIC/TPU Focus

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Bonus

Benefits

Job summary

Google Inc. in Sunnyvale, CA, is seeking a Mid-level RTL Design Engineer to shape the TPU architecture for ML accelerators. The role focuses on designing and verifying complex digital blocks and collaborating with software teams to ensure robust interfaces and integration.

You will contribute to high-performance, low-power AI hardware while participating in the broader AI/ML hardware ecosystem at Google.

Qualifications

• Bachelor’s degree in EE/CE/CS or related field.
• 4 years of experience with custom silicon design (SoCs, ASICs, etc.).
• Experience with RTL design using Verilog or SystemVerilog.

Responsibilities

• Understand the overall application of the chip, proposing and developing improvements in overall design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on functionality, interfaces, and documentation.

Skills

RTL design

Verilog/SystemVerilog

Python/Perl

Education

Bachelor's degree in EE/CE/CS or related

4 years of custom silicon design experience

Tools

Python

Perl

Job description

Google Inc. in Sunnyvale, CA, is seeking a Mid-level RTL Design Engineer to shape the TPU architecture for ML accelerators. The role focuses on designing and verifying complex digital blocks and collaborating with software teams to ensure robust interfaces and integration.

You will contribute to high-performance, low-power AI hardware while participating in the broader AI/ML hardware ecosystem at Google.