AI/ML Accelerator RTL Design Engineer

Socket.dev; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Bonus target

Job summary

Google is seeking a hardware design engineer to advance TPU architecture and accelerator technology. You will verify complex digital designs and contribute to silicon solutions powering AI/ML workloads.

The role emphasizes RTL coding in Verilog/SystemVerilog, ASIC/SoC design, and collaboration with software and architecture teams to optimize performance and power for large-scale AI systems.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 4 years of experience with custom silicon design (SoCs/ASICs).
• Experience with RTL design using Verilog or SystemVerilog.

Responsibilities

• Understand the overall application of the chip and propose improvements to the design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on interfaces and documentation.

Skills

RTL design (Verilog/SystemVerilog)

custom silicon design

Education

Bachelor's degree in EE/CE/CS or related field

Job description

Google is seeking a hardware design engineer to advance TPU architecture and accelerator technology. You will verify complex digital designs and contribute to silicon solutions powering AI/ML workloads.

The role emphasizes RTL coding in Verilog/SystemVerilog, ASIC/SoC design, and collaboration with software and architecture teams to optimize performance and power for large-scale AI systems.