ASIC Power Architect for ML Accelerators

Socket.dev; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus program (15% target)

Comprehensive benefits

Job summary

Google in Sunnyvale seeks an ASIC Design Engineer to shape AI/ML hardware acceleration. You will drive TPU power modeling and convergence to power goals, and verify complex digital designs with a focus on TPU architecture integration for AI/ML systems.

You will contribute to power efficiency for TPUs, build power models, and explore optimization techniques while collaborating with cross-functional teams on data-center accelerators. Equity and benefits offered.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CS/related field.
• 8 years of experience in silicon design or architecture (logic design, power, SoC).
• Experience with power design, power modeling, power architecture, or power reduction methodologies.

Responsibilities

• Contribute to design power modeling and drive convergence to power goals.
• Investigate and deploy architectural and microarchitectural power optimization techniques.
• Define best practices to achieve low-power designs.
• Collaborate with software and system teams to create power management architectures meeting power goals.

Skills

Power design

Power modeling

Power architecture

Power reduction techniques

Chip power management

Education

Bachelor's degree in Electrical Engineering/CS/related field

Master's or PhD preferred (Electrical/CS)

Job description

Google in Sunnyvale seeks an ASIC Design Engineer to shape AI/ML hardware acceleration. You will drive TPU power modeling and convergence to power goals, and verify complex digital designs with a focus on TPU architecture integration for AI/ML systems.

You will contribute to power efficiency for TPUs, build power models, and explore optimization techniques while collaborating with cross-functional teams on data-center accelerators. Equity and benefits offered.