Memory Subsystem RTL Engineer: High-Speed, Low-Power SoC

Velaura; Santa Clara (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Equity compensation

Medical benefits

Paid time off

Job summary

Velaura is seeking an RTL Engineer to shape the memory subsystem of the next-generation Physical AI SoC in Santa Clara, CA. You will work with architects, performance modelers, software and verification teams to translate architectural concepts into production silicon.

The role focuses on high-speed, low-power memory paths, including controllers, interconnects, calibration, DVFS, and ECC. You will own design decisions, drive timing closure, and collaborate across memory IP partners and vendors

Qualifications

• Hands-on RTL design for memory subsystem blocks.
• Experience integrating a memory controller with a memory PHY (DFI, bring-up).
• Strong knowledge of LPDDR4/4X/5/5X, DDR, and HBM memory technologies and power-state behavior.
• Expert-level Verilog/SystemVerilog and RTL design methodologies.
• Ability to optimize for performance, power and area.
• Proven debugging and cross-functional collaboration skills.

Responsibilities

• Design, implement, and optimize RTL for the memory subsystem.
• Own memory controller and PHY integration including DFI, init and training flows.
• Drive high-speed, low-power memory path design and DVFS interactions.
• Define hardware interfaces, memory maps, and performance-critical interactions.
• Analyze bottlenecks and propose architectural improvements.
• Collaborate with verification, physical design, memory IP and vendors.
• Leverage AI-assisted workflows to improve productivity.
• Participate in design reviews and maintain technical excellence.

Skills

RTL design

Memory subsystem

Verilog SystemVerilog

DFI interfaces

Performance optimization

Debugging

Cross-team collaboration

Tools

Memory PHY bring-up

Job description

Velaura is seeking an RTL Engineer to shape the memory subsystem of the next-generation Physical AI SoC in Santa Clara, CA. You will work with architects, performance modelers, software and verification teams to translate architectural concepts into production silicon.

The role focuses on high-speed, low-power memory paths, including controllers, interconnects, calibration, DVFS, and ECC. You will own design decisions, drive timing closure, and collaborate across memory IP partners and vendors