RTL Power Engineer for Next-Gen Physical AI SoC

Velaura AI, Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 200,000 - 350,000; Full time

Benefits offered by this job

Equity participation

Flexible work arrangements

Professional development opportunities

Medical, dental, vision coverage

Paid time off

Job summary

Velaura AI, Inc. seeks an RTL Engineer to own power management for the next-generation Physical AI SoC in Santa Clara. You will work with architects, performance modelers, software, verification, and physical design teams to translate concepts into production silicon.

You will own power management at every level, delivering silicon that meets performance targets within allocated budgets, while collaborating across teams on DVFS, clocking, and telemetry.

Qualifications

• BS or higher in Electrical Engineering, Computer Engineering or a related field.
• Strong grasp of power, thermal, and voltage droop concepts impacting timing.
• Experience designing SoC power management hardware and verification workflows.

Responsibilities

• Design on-chip power management hardware including meters and throttlers.
• Implement temperature sensor controls to maintain defined thermal limits.
• Develop power and activity limit controls and di/dt protections.
• Collaborate with architects, physical design, and package teams on power delivery.
• Own clock and reset architecture, including gating and PLL management.
• Define power state management with DVFS and retention flows.
• Correlate RTL, emulation and silicon power estimates; build telemetry.
• Work with firmware/software on interfaces and telemetry for power/thermal management.

Skills

Power management design

RTL design

Verilog/SystemVerilog

Power estimation & analysis

HW/SW debugging

Clock and reset architecture

Thermal & di/dt concepts

Voltage droop & PDN behavior

Education

BS in Electrical Engineering or Computer Engineering

Tools

PowerArtist

PrimePower

Joules

UPF

Job description

Velaura AI, Inc. seeks an RTL Engineer to own power management for the next-generation Physical AI SoC in Santa Clara. You will work with architects, performance modelers, software, verification, and physical design teams to translate concepts into production silicon.

You will own power management at every level, delivering silicon that meets performance targets within allocated budgets, while collaborating across teams on DVFS, clocking, and telemetry.