Senior Memory Subsystem RTL Architect for AI Chips

Architect Labs; Palo Alto, Northern (CA, KY); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Architect Labs seeks a founding member for RTL design of the memory subsystem powering AI workloads. You will own memory controllers, hierarchy, and near-memory accelerators, collaborating with DV, SW, and ML teams to hit bandwidth, latency, and power goals.

Strong SystemVerilog, DDR/HBM knowledge, and Python tooling are essential, with experience in high-frequency controller logic and tapeouts.

Qualifications

• Experience with memory subsystems including DDR/LPDDR/HBM controllers.
• Hands-on RTL design for memory controllers and cache hierarchies.
• Prototyping experience with FPGA hardware platforms is a plus.

Responsibilities

• Own the memory subsystem RTL end-to-end from spec to tapeout.
• Design and implement memory controllers and scheduling policies.
• Architect multi-level memory hierarchy and memory-side accelerators.
• Collaborate with DV, SW, and ML teams to optimize memory workloads.

Skills

RTL design

SystemVerilog

memory controllers

cache hierarchy

AXI/ACE/CHI

PPA ownership

Python

HDL coding practices

Education

Bachelor’s/Master’s/PhD in Electrical Engineering or Computer Engineering

Tools

Xilinx Vivado

DDR MIG IP

SVA tooling / verification

Ramulator/DRAMSim

Job description

Architect Labs seeks a founding member for RTL design of the memory subsystem powering AI workloads. You will own memory controllers, hierarchy, and near-memory accelerators, collaborating with DV, SW, and ML teams to hit bandwidth, latency, and power goals.

Strong SystemVerilog, DDR/HBM knowledge, and Python tooling are essential, with experience in high-frequency controller logic and tapeouts.