RTL Memory Subsystem Architect for AI Chips

Architect; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Architect Labs is seeking a Technical Staff member in Palo Alto to own the memory subsystem RTL end-to-end for production silicon. You’ll architect controllers for DDR5/LPDDR5X and HBM3, drive timing closure, and collaborate with DV, SW, and ML teams.

You’ll refine memory hierarchy, implement near-memory accelerators, and ensure bandwidth, latency, and power targets are met in ML workloads. Strong SystemVerilog and PPA ownership are essential.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical/Computer Engineering or related field.
• 5+ years RTL design with memory subsystems tapeout experience.
• Deep familiarity with JEDEC memory standards (DDR5/LPDDR5X, HBM2E/3).
• Hands-on memory controller design (schedulers, refresh engines, ECC).
• Experience with memory hierarchy, cache, QoS and timing constraints.
• Strong SystemVerilog for multi-standard support and RTL modularity.

Responsibilities

• Own the memory subsystem RTL end-to-end, from design through timing closure.
• Design/implement memory controllers for DDR5/LPDDR5X and HBM3 pseudo-channels.
• Architect memory hierarchy with caches, scratchpad, and QoS.
• Develop memory-side accelerators and data-path interfaces (AXI/ACE/CHI).
• Collaborate with DV, SW and ML teams and support FPGA prototyping.

Skills

RTL design

SystemVerilog

Python

PPA ownership

Memory subsystem

Education

Bachelor’s / Master’s / PhD in EE/CE

Tools

DFI

JEDEC memory standards

DDR5/HBM3 memory

Xilinx Vivado/Vitis

Job description

Architect Labs is seeking a Technical Staff member in Palo Alto to own the memory subsystem RTL end-to-end for production silicon. You’ll architect controllers for DDR5/LPDDR5X and HBM3, drive timing closure, and collaborate with DV, SW, and ML teams.

You’ll refine memory hierarchy, implement near-memory accelerators, and ensure bandwidth, latency, and power targets are met in ML workloads. Strong SystemVerilog and PPA ownership are essential.