Principal RTL Design Engineer High-Perf Memory Controllers

Lumicity; San Francisco (CA); On-site; USD 180,000 - 270,000; Full time

Job summary

Lumicity in San Francisco is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL design of next-generation, high-performance memory controllers powering data centers and AI applications. You will own end-to-end microarchitecture & RTL, drive PPA and silicon success, and collaborate with verification, physical design, and cross-functional teams to deliver robust designs.

The ideal candidate has 10+ years in ASIC/FPGA, strong SystemVerilog/Verilog, and memory interface

Qualifications

• 10+ years ASIC/FPGA design with SystemVerilog/Verilog RTL and strong EE foundation.
• Hands-on verification & scripting across Questa/Incisive/VCS, UVM, Python, Perl & TCL.
• Silicon‑savvy design with synthesis, timing constraints, CDC/RDC, and PPA‑aware implementation.
• Bonus: memory interfaces AMBA AXI/CHI, HBM, LPDDR; strong communication and problem-solving.

Responsibilities

• Own end-to-end microarchitecture & RTL for critical, high-performance SoC blocks
• Drive PPA and silicon success through data-driven performance, power, timing, and area optimization
• Partner across verification & physical design to solve complex issues and deliver robust, production-ready designs
• Influence customer success by providing hands-on technical leadership from pre-sales through post-sales delivery

Skills

SystemVerilog/Verilog RTL

Verification scripting

PPA-aware design

Memory interfaces

Tools

Questa/Incisive/VCS

UVM

Python

Perl

TCL

Job description

Lumicity in San Francisco is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL design of next-generation, high-performance memory controllers powering data centers and AI applications. You will own end-to-end microarchitecture & RTL, drive PPA and silicon success, and collaborate with verification, physical design, and cross-functional teams to deliver robust designs.

The ideal candidate has 10+ years in ASIC/FPGA, strong SystemVerilog/Verilog, and memory interface