RTL Engineer Memory Subsystem

Velaura; Santa Clara (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Equity compensation

Medical benefits

Paid time off

Job summary

Velaura is seeking an RTL Engineer to shape the memory subsystem of the next-generation Physical AI SoC in Santa Clara, CA. You will work with architects, performance modelers, software and verification teams to translate architectural concepts into production silicon.

The role focuses on high-speed, low-power memory paths, including controllers, interconnects, calibration, DVFS, and ECC. You will own design decisions, drive timing closure, and collaborate across memory IP partners and vendors

Qualifications

• Hands-on RTL design for memory subsystem blocks.
• Experience integrating a memory controller with a memory PHY (DFI, bring-up).
• Strong knowledge of LPDDR4/4X/5/5X, DDR, and HBM memory technologies and power-state behavior.
• Expert-level Verilog/SystemVerilog and RTL design methodologies.
• Ability to optimize for performance, power and area.
• Proven debugging and cross-functional collaboration skills.

Responsibilities

• Design, implement, and optimize RTL for the memory subsystem.
• Own memory controller and PHY integration including DFI, init and training flows.
• Drive high-speed, low-power memory path design and DVFS interactions.
• Define hardware interfaces, memory maps, and performance-critical interactions.
• Analyze bottlenecks and propose architectural improvements.
• Collaborate with verification, physical design, memory IP and vendors.
• Leverage AI-assisted workflows to improve productivity.
• Participate in design reviews and maintain technical excellence.

Skills

RTL design

Memory subsystem

Verilog SystemVerilog

DFI interfaces

Performance optimization

Debugging

Cross-team collaboration

Tools

Memory PHY bring-up

Job description

Role Overview

We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip.

In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP and PHY partners to transform innovative architectural concepts into production silicon. You will own significant portions of the memory subsystem design, contribute to microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems.

Physical AI workloads are memory-bound: bandwidth, latency, and power in the memory path directly gate what the chip can do. If pushing modern memory technologies to their limits at high speed and low power is the kind of problem you want to own, this role is for you.

Responsibilities

• Design, implement, and optimize RTL for the memory subsystem of the Velaura SoC, including memory controllers, fabric interfaces, and the logic that integrates with external memory PHYs.
• Own memory controller and PHY integration, including controller-to-PHY interfaces such as DFI, initialization and training flows, calibration, and bring-up hooks.
• Drive high-speed, low-power design of the memory path, including timing closure at high data rates, power-state management such as self-refresh and power-down modes, clock and power gating, and DVFS interactions.
• Work with software teams to define hardware interfaces, memory maps, execution flows, and performance-critical interactions such as scheduling, prefetching, and quality of service.
• Analyze bandwidth, latency, and utilization bottlenecks in the memory path and propose architectural and implementation improvements.
• Optimize designs for performance, power, area, scalability, and reliability, including RAS features such as ECC and error reporting in the memory path.
• Partner closely with verification and physical design teams throughout the development cycle, and with memory IP and PHY vendors during integration and silicon bring-up.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in design reviews and contribute to a culture of technical excellence.

Required Qualifications

• Experience designing RTL for complex digital systems, with hands‑on ownership of memory subsystem blocks.
• Demonstrated experience integrating a memory controller with a memory PHY, including controller‑to‑PHY interfaces such as DFI, initialization and training sequences, and bring‑up.
• Strong understanding of high-speed, low‑power memory technologies such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, and HBM, including their protocol, timing, and power‑state behavior.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Expert‑level Verilog and SystemVerilog skills and experience with modern RTL design methodologies, including lint, clock‑domain crossing analysis, synthesis‑aware coding, and low‑power intent.
• Familiarity with performance, power, and area tradeoffs in the memory path.
• Strong debugging and problem‑solving skills.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

• Familiarity with standard interconnect protocols such as AXI, CHI, and ACE on the controller's system‑side interface, including quality‑of‑service mechanisms.
• Experience with memory controller and PHY bring‑up on silicon, including training and calibration debug and margining.
• Knowledge of reliability, availability, and serviceability in the memory path, including inline and side‑band ECC, scrubbing, poisoning, and error reporting.
• Experience with low‑power design techniques and power management architectures across memory and clock and power domains.
• Experience developing a memory controller from the ground up, including command scheduling and arbitration, bank and rank management, refresh management, and reordering.
• Knowledge of functional safety standards such as ISO 26262 and ASIL as they apply to memory‑path design.
• Experience with AI, machine learning, or edge AI hardware, especially the memory access patterns of tensor workloads.
• Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
• Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring‑up.
• Experience using modern AI tools and workflows to accelerate engineering productivity.

$150,000 - $250,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long‑term success.

The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate's skills, qualifications, relevant experience, and geographic location.

In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well‑being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next‑generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry‑defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: [e-mail]. This contact
information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case‑by‑case basis.