Memory PHY RTL Design Engineer – DDR/LPDDR Expert (Hybrid)

Dexian; Massachusetts; Hybrid; USD 96,000 - 152,000; Full time

Job summary

Dexian is seeking an ASIC RTL Design Engineer focusing on Memory PHY in Boxborough, MA. This is a hybrid contract role with an initial 12+ months. The ideal candidate will bring strong experience in ASIC/Digital Design, RTL coding (Verilog/SystemVerilog), C/C++, along with Synthesis, Timing Closure, and CDC expertise.

Nice-to-have skills include DDR/LPDDR memory interfaces, Memory PHY design, high-speed interfaces, and scripting in Python and TCL to automate flows.

Qualifications

• Must have strong ASIC/Digital Design, RTL Coding (Verilog/SystemVerilog), C/C++, Synthesis, Timing Closure, and CDC experience.
• Plus: DDR/LPDDR, Memory PHY, high-speed interface design, and Python/TCL scripting.

Skills

ASIC/Digital Design

RTL Coding (Verilog/SystemVerilog)

Verilog/SystemVerilog

C/C++

Synthesis

Timing Closure

CDC

Python

TCL scripting

Memory PHY

DDR/LPDDR

High-speed interface design

Job description

Dexian is seeking an ASIC RTL Design Engineer focusing on Memory PHY in Boxborough, MA. This is a hybrid contract role with an initial 12+ months. The ideal candidate will bring strong experience in ASIC/Digital Design, RTL coding (Verilog/SystemVerilog), C/C++, along with Synthesis, Timing Closure, and CDC expertise.

Nice-to-have skills include DDR/LPDDR memory interfaces, Memory PHY design, high-speed interfaces, and scripting in Python and TCL to automate flows.