Hardware Design Engineer

TPI Global Solutions; Boxborough (MA); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

TPI Global Solutions in Boxborough, MA is seeking a Design Engineer to drive RTL and firmware development for high-speed LPDDR, DDR memory IP. The role involves defining, designing and implementing IO designs and collaborating across RTL, firmware, analog, and architecture teams to deliver industry-leading memory interfaces.

You will work on clocking architectures, timing closure, and verification using simulation tools, with demand for strong English communication and ability to mentor

Formación

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

Responsabilidades

• RTL design for memory I/O.
• PHY Digital Architecture development from pathfinding to physical implementation.
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design.
• Digital design and RTL coding.
• Timing Synthesis & Drive Physical implementation.
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build the unit tests.
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues.

Conocimientos

Verilog

SystemVerilog

C

C++

Python/TCL scripting

Educación

Bachelor's or Master’s in Electrical/Computer Engineering

Herramientas

Simulation tools

Synthesis tools

Descripción del empleo

Duration: 12 Month Contract with possible extension

Location: Boxborough, MA (Onsite)

Description: THE ROLE:

• The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.
• THE PERSON:
• You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• RTL design for memory I/O
• PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the unit tests
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE:

• Experienced with Verilog, System Verilog, C, and C++
• Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
• Knowledge of clocking architectures, synchronization, and CDC methodology
• Experience with synthesis, Timing closure
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Proficient in debugging firmware and RTL code using simulation tools
• Strong understanding of computer organization/architecture.
• Mixed signal RTL, Low power design experience is a plus
• Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering