Memory I/O RTL Design Engineer (DDR/LPDDR)

LanceSoft, Inc.; Boxborough (MA); On-site; USD 120,000 - 190,000; Full time

Job summary

LanceSoft, Inc. is seeking an RTL Design Engineer for Memory I/O level-2 in Boxborough, MA. You will contribute to RTL and firmware development for high-speed LPDDR and DDR IPs, shaping the design from architecture to verification.

The role involves creating new IO designs and improving methodologies across multiple designs. The candidate will work closely with RTL, FW, analog and architecture teams to deliver industry-leading IP, execute timing closure, and optimize for performance while

Qualifications

• Requires experience with Verilog and SystemVerilog in RTL/firmware development.
• Experience with memory interfaces and IPs (DDR/LPDDR, SERDES) preferred.
• Familiarity with timing, synthesis, and CDC methodologies is expected.

Responsibilities

• RTL design for memory I/O and PHY digital architecture development.
• Collaborate with architects, hardware and firmware engineers on new features.
• Write and verify tests, build unit tests, and drive test environments.
• Debug design failures and resolve defects with DV/firmware teams.

Skills

Verilog

SystemVerilog

C

C++

Python

Perl

TCL

Clocking architectures

Synthesis

Timing closure

DDR/LPDDR

Memory Controller

MAC Design

Debugging firmware and RTL

Architecture knowledge

Leadership/mentorship

Education

Bachelors or Masters degree in computer engineering/Electrical Engineering

Tools

Python

Perl

TCL

Job description

LanceSoft, Inc. is seeking an RTL Design Engineer for Memory I/O level-2 in Boxborough, MA. You will contribute to RTL and firmware development for high-speed LPDDR and DDR IPs, shaping the design from architecture to verification.

The role involves creating new IO designs and improving methodologies across multiple designs. The candidate will work closely with RTL, FW, analog and architecture teams to deliver industry-leading IP, execute timing closure, and optimize for performance while