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Dexian is seeking an ASIC RTL Design Engineer specializing in Memory PHY for a hybrid role in Boxborough, MA. The contract is 12+ months, with duties centered on ASIC digital design, Verilog/SystemVerilog RTL coding, and memory interface work.
The position supports DDR/LPDDR memory interfaces, high-speed design, and scripting with Python/TCL. Dexian emphasizes equal opportunity employment and global staffing expertise.
Boxborough, MA (Hybrid)
12 + Months
Must have strong ASIC/Digital Design, RTL Coding (Verilog/SystemVerilog), C/C++, Synthesis, Timing Closure, and CDC experience.
Plus: DDR/LPDDR, Memory PHY, high-speed interface design, and Python/TCL scripting.
Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.
Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals. To learn more, please visit https://dexian.com/.
Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.