Lead ASIC Digital Design Engineer for LPDDR PHY

Synopsys Inc; Sunnyvale (CA); On-site; USD 170,000 - 210,000; Full time

Job summary

Synopsys Inc. is seeking an experienced ASIC digital design engineer to own RTL for LPDDR PHY IP. You will design RTL modules from microarchitecture through synthesis-ready implementation and optimize for timing, power, and area across multiple nodes.

You will develop Perl automation for design generation, collaborate with cross-functional teams, and contribute to design reviews. A strong background in Verilog, synthesis, and timing analysis is required, with 8+ years in production silicon.

Qualifications

• 8+ years of ASIC digital design experience with RTL ownership in production silicon.
• Expert Verilog proficiency for timing-critical designs.
• Deep knowledge of synthesis, timing analysis, and power optimization.

Responsibilities

• Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation.
• Optimize designs to meet timing, power, and area targets across multiple process nodes.
• Develop Perl automation for design generation and flow integration.
• Collaborate with cross-functional teams to resolve timing and power challenges.
• Contribute to design reviews and methodology development.

Skills

RTL ownership

Verilog

Timing analysis

Power optimization

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Perl scripting

Synthesis tools

Job description

Synopsys Inc. is seeking an experienced ASIC digital design engineer to own RTL for LPDDR PHY IP. You will design RTL modules from microarchitecture through synthesis-ready implementation and optimize for timing, power, and area across multiple nodes.

You will develop Perl automation for design generation, collaborate with cross-functional teams, and contribute to design reviews. A strong background in Verilog, synthesis, and timing analysis is required, with 8+ years in production silicon.