Senior RTL Design Engineer - DDR/LPDDR Memory Controller

AMD; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

AMD in Austin, TX, is seeking an RTL Design Engineer to join the Memory Controller Design team. You will contribute to IP microarchitecture features and develop RTL for IP blocks with focus on power, performance, and area optimization.

You will collaborate with architects and verification engineers across global teams, perform lint, CDC, timing analysis, and participate in design and code reviews to ensure high-quality IP implementations in a fast-paced engineering environment.

Qualifications

• Bachelor’s or master’s degree in computer engineering, electrical engineering, computer science, or a related technical field.
• Experience with IP microarchitecture and RTL design preferred.
• Strong written and verbal communication skills.

Responsibilities

• Work closely with architects to define and implement IP microarchitecture features
• Develop RTL designs for IP features
• Analyze and optimize designs for power, performance, and area
• Participate in design specification reviews and code reviews
• Perform lint, CDC, and timing analysis to support high‑quality design implementation
• Collaborate with verification engineers to validate and debug IP throughout the project lifecycle

Skills

Digital logic design

Verilog/SystemVerilog

Python

Perl

Tcl

Computer architecture

DDR/LPDDR

EDA tools

Digital verification

Independent worker

Communication skills

Education

Bachelor’s or Master’s in Computer Engineering, Electrical Engineering, or Computer Science

Tools

HDL simulators

Synthesis tools

Job description

AMD in Austin, TX, is seeking an RTL Design Engineer to join the Memory Controller Design team. You will contribute to IP microarchitecture features and develop RTL for IP blocks with focus on power, performance, and area optimization.

You will collaborate with architects and verification engineers across global teams, perform lint, CDC, timing analysis, and participate in design and code reviews to ensure high-quality IP implementations in a fast-paced engineering environment.