ASIC RTL Design Engineer - Memory PHY (Hybrid, MA)

Dexian; Maynard (MA); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Dexian is seeking an ASIC RTL Design Engineer specializing in Memory PHY for a hybrid role in Boxborough, MA. The contract is 12+ months, with duties centered on ASIC digital design, Verilog/SystemVerilog RTL coding, and memory interface work.

The position supports DDR/LPDDR memory interfaces, high-speed design, and scripting with Python/TCL. Dexian emphasizes equal opportunity employment and global staffing expertise.

Qualifications

• Must have strong ASIC/Digital Design, RTL Coding (Verilog/SystemVerilog), C/C++, Synthesis, Timing Closure, and CDC experience.

Skills

ASIC Design

RTL Verilog

Synthesis

Timing Closure

CDC

C/C++

Memory PHY

DDR/LPDDR

Python TCL

High-speed interface

Job description

Dexian is seeking an ASIC RTL Design Engineer specializing in Memory PHY for a hybrid role in Boxborough, MA. The contract is 12+ months, with duties centered on ASIC digital design, Verilog/SystemVerilog RTL coding, and memory interface work.

The position supports DDR/LPDDR memory interfaces, high-speed design, and scripting with Python/TCL. Dexian emphasizes equal opportunity employment and global staffing expertise.