RTL Design Engineer for Memory I/O level-2

LanceSoft, Inc.; Boxborough (MA); On-site; USD 120,000 - 190,000; Full time

Job summary

LanceSoft, Inc. is seeking an RTL Design Engineer for Memory I/O level-2 in Boxborough, MA. You will contribute to RTL and firmware development for high-speed LPDDR and DDR IPs, shaping the design from architecture to verification.

The role involves creating new IO designs and improving methodologies across multiple designs. The candidate will work closely with RTL, FW, analog and architecture teams to deliver industry-leading IP, execute timing closure, and optimize for performance while

Qualifications

• Requires experience with Verilog and SystemVerilog in RTL/firmware development.
• Experience with memory interfaces and IPs (DDR/LPDDR, SERDES) preferred.
• Familiarity with timing, synthesis, and CDC methodologies is expected.

Responsibilities

• RTL design for memory I/O and PHY digital architecture development.
• Collaborate with architects, hardware and firmware engineers on new features.
• Write and verify tests, build unit tests, and drive test environments.
• Debug design failures and resolve defects with DV/firmware teams.

Skills

Verilog

SystemVerilog

C

C++

Python

Perl

TCL

Clocking architectures

Synthesis

Timing closure

DDR/LPDDR

Memory Controller

MAC Design

Debugging firmware and RTL

Architecture knowledge

Leadership/mentorship

Education

Bachelors or Masters degree in computer engineering/Electrical Engineering

Tools

Python

Perl

TCL

Job description

Job Title - RTL Design Engineer for Memory I/O level-2

Job Location - Boxborough-MA

Job Description -

Description: THE ROLE:

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

RESPONSIBILITIES:

• RTL design for memory I/O
• PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the unit tests
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE:

• Experienced with Verilog, System Verilog, C, and C++
• Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
• Knowledge of clocking architectures, synchronization, and CDC methodology
• Experience with synthesis, Timing closure
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Proficient in debugging firmware and RTL code using simulation tools
• Strong understanding of computer organization/architecture.
• Mixed signal RTL, Low power design experience is a plus
• Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering