Memory Controller IP Verification Engineer

ARM; Austin (TX); On-site; USD 250,000 - 338,000; Full time

Job summary

Arm is seeking a Design Verification Engineer to join the Memory Controller IP verification team. You will develop verification strategies and SystemVerilog/UVM environments to validate functionality, performance, and protocol behaviour across supported memory technologies.

Collaborate with RTL designers, architects, and verification colleagues to investigate issues, support verification closure for features, and deliver high-quality IP on schedule.

Qualifications

• Practical experience verifying ASIC or SoC designs using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.
• Ability to develop verification plans and translate architectural specifications into tests, coverage, and verification environments.
• Understanding of memory controller architecture and memory protocol concepts, including LPDDR or DDR technologies.
• Ability to debug RTL, testbench, and protocol issues using simulation tools, waveforms, and logs, and communicate findings clearly with cross-functional teams.

Responsibilities

• Develop and maintain SystemVerilog/UVM verification environments for Memory Controller IP.
• Create verification plans, test scenarios, assertions, functional coverage models, and scoreboards from architectural specifications.
• Develop constrained-random and directed tests to verify memory controller functionality across supported LPDDR and DDR technologies.
• Analyse regressions, coverage, simulation waveforms, and logs to identify RTL, testbench, and protocol issues.
• Partner with RTL designers, architects, and verification teams to clarify behaviour, resolve issues, and support verification sign-off.
• Improve verification efficiency through scripting, automation, and verification methodology improvements.
• Take ownership of assigned features and deliver verification milestones to agreed schedules.

Skills

SystemVerilog/UVM verification

Test plan development

Memory controller architectures

RTL/testbench/protocol debugging

Tools

Synopsys VCS

Siemens Questa

DFI 4.x/5.x

AMBA AXI/ACE/CHI

Job description

Arm is seeking a Design Verification Engineer to join the Memory Controller IP verification team. You will develop verification strategies and SystemVerilog/UVM environments to validate functionality, performance, and protocol behaviour across supported memory technologies.

Collaborate with RTL designers, architects, and verification colleagues to investigate issues, support verification closure for features, and deliver high-quality IP on schedule.