Senior Design Verification Architect - Memory/NoC Lead

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

AMD Benefits at a glance

Job summary

AMD's Adaptive and Embedded Computing Group seeks a Senior Staff Silicon Design Verification Engineer to lead verification of high‑speed Crypto, NoC, and memory controller IPs (DDR5, LPDDR6, HBM4) for next‑gen devices. You will architect verification environments at IP and SoC levels and drive plans and strategies with a focus on first‑pass silicon success.

The ideal candidate has 5+ engineers led, strong leadership, and hands‑on experience with UVM, SystemVerilog, and formal methods.

Qualifications

• BS in Electrical Engineering or related field with 8+ years of experience, MS with 6+ years, or PhD with 3+ years.
• Experience verifying memory controllers (DDR/LPDDR/HBM) and NoC/crypto IPs.
• Proven leadership of verification teams (5+ engineers) and project delivery.

Responsibilities

• Lead verification of high-speed Crypto, NoC, and memory controller designs (DDR5/LPDDR6/HBM4).
• Architect and implement IP- and SoC-level verification environments.
• Manage verification planning, execution, and closure; drive programs to on-time delivery.
• Develop tests, testbenches, and coverage strategies; mentor junior engineers.

Skills

UVM

SystemVerilog

Verification leadership

VCS/Xcelium

Education

BS in Electrical Engineering

MS in Electrical Engineering

PhD in Computer Science/Engineering

Tools

Synopsys VCS

Cadence Xcelium

VC Formal/JasperGold/Questa Formal

Job description

AMD's Adaptive and Embedded Computing Group seeks a Senior Staff Silicon Design Verification Engineer to lead verification of high‑speed Crypto, NoC, and memory controller IPs (DDR5, LPDDR6, HBM4) for next‑gen devices. You will architect verification environments at IP and SoC levels and drive plans and strategies with a focus on first‑pass silicon success.

The ideal candidate has 5+ engineers led, strong leadership, and hands‑on experience with UVM, SystemVerilog, and formal methods.