Senior Design Verification Engineer

ACL Digital; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

ACL Digital is seeking a verification engineer focused on HBM-based memory controller verification. The role requires strong SystemVerilog/UVM expertise and experience validating DDR/HBM memory controllers, plus knowledge of HBM/DDR protocols and AXI interfaces.

You will develop UVM testbenches, assertions, and coverage plans, run regressions, and collaborate with Architecture, RTL, and Validation teams to achieve signoff on verification results.

Qualifications

• Strong SystemVerilog/UVM expertise.
• Experience verifying DDR/HBM memory controllers or memory subsystems.
• Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficiency with scripting (Python/Perl/Shell).

Responsibilities

• Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Skills

SystemVerilog/UVM

Memory controller verification

HBM/DDR protocols

AXI interfaces

Scripting (Python/Perl/Shell)

Tools

Xcelium/VCS/Questa

Job description

• Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Required Skills

• Strong SystemVerilog/UVM expertise.
• Experience verifying DDR/HBM memory controllers or memory subsystems.
• Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).