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ACL Digital is seeking a verification engineer focused on HBM-based memory controller verification. The role requires strong SystemVerilog/UVM expertise and experience validating DDR/HBM memory controllers, plus knowledge of HBM/DDR protocols and AXI interfaces.
You will develop UVM testbenches, assertions, and coverage plans, run regressions, and collaborate with Architecture, RTL, and Validation teams to achieve signoff on verification results.
ACL Digital is seeking a verification engineer focused on HBM-based memory controller verification. The role requires strong SystemVerilog/UVM expertise and experience validating DDR/HBM memory controllers, plus knowledge of HBM/DDR protocols and AXI interfaces.
You will develop UVM testbenches, assertions, and coverage plans, run regressions, and collaborate with Architecture, RTL, and Validation teams to achieve signoff on verification results.