CPU Memory-Systems Verification Engineer

ARM; Chandler (AZ); On-site; USD 130,000 - 176,000; Full time

Job summary

Arm in Chandler is seeking a skilled CPU verification engineer to join the Chandler-based verification team. You will help verify Cortex-A designs, focusing on memory-system blocks and high-quality CPU IP used across devices.

You will collaborate with architects and verification engineers, applying simulation and formal verification techniques to investigate complex design behaviour and improve verification environments.

Qualifications

• Experience in pre-silicon design verification and RTL testbenches.
• Knowledge of CPU memory-subsystem microarchitecture (load/store, L2, MMUs).
• Experience using simulation and/or formal verification methods to verify hardware.
• OO programming skills and proficiency in SystemVerilog/UVM.

Responsibilities

• Develop SystemVerilog UVM and formal verification environments and tests for block-level verification.
• Create and maintain verification plans for assigned functional blocks to ensure quality across engineering phases.
• Generate and run tests on logic simulation models; investigate and debug RTL issues using simulation/debug tools.
• Define and implement functional and statistical coverage; improve testbenches and drive coverage closure.
• Work closely with design and architecture to understand CPU memory-system behaviour and resolve verification issues.

Skills

SystemVerilog

UVM

Formal verification

OO programming

Memory-subsystem knowledge

Education

Bachelor’s or Master’s degree in CS/EE/CE

Tools

SystemVerilog

UVM

Formal verification tools

Job description

Arm in Chandler is seeking a skilled CPU verification engineer to join the Chandler-based verification team. You will help verify Cortex-A designs, focusing on memory-system blocks and high-quality CPU IP used across devices.

You will collaborate with architects and verification engineers, applying simulation and formal verification techniques to investigate complex design behaviour and improve verification environments.