Senior System IP Verification Engineer

NuByt, Inc; Texas; On-site; USD 140,000 - 190,000; Full time

Job summary

NuByt, Inc. is seeking a Senior Staff System IP Design Verification Engineer/Consultant to drive functional verification of System IP, including coherent interconnects and caches.

This highly technical role demands hands-on verification expertise at block- and top-level levels. You will develop verification environments, debug complex functional failures, run gate-level simulations, and drive coverage closure.

Qualifications

• Bachelor's/Master's/Ph.D. in EE/CE or related field.
• 12+ years of industry experience in design verification.
• Expert hands-on coding in testbench development, stimulus generation, checkers, and coverage closure.
• Strong experience with SystemVerilog and UVM or equivalent verification methodologies.
• 5+ years of hands-on experience with gate-level simulations.
• Strong knowledge of ARM protocols (CHI, AXI, ACE-Lite, APB).

Responsibilities

• Own gate-level simulation testbench bring-up and debugging.
• Own power-aware verification using UPF.
• Collaborate with Physical Design teams to run and debug gate-level simulations.
• Work closely with SoC teams to debug functional failures during IP bring-up and feature execution.
• Create and maintain testbenches, verification environments, stimulus, and tests.
• Collaborate with RTL/design engineers to verify design features and resolve functional failures.
• Develop SystemVerilog assertions, checkers, covergroups, and constraints.
• Debug and root‑cause functional failures from regression testing.
• Analyze code coverage and functional coverage and perform coverage gap analysis.
• Support silicon bring-up and root‑cause hardware/functional failures.
• Contribute to verification strategy, execution, and overall coverage closure.

Skills

Testbench development

Stimulus generation

Checkers

Coverage closure

SystemVerilog

UVM

Gate-level simulations

Scripting

Communication

IP verification

Education

Electrical/Computer Engineering degree

Tools

Git

Unix/Linux

Python

Perl

Job description

Job Description

Job Description

We are seeking a highly experienced Senior Staff System IP Design Verification Engineer/Consultant to contribute to the functional verification of System IP, including coherent interconnects and caches. This is a highly technical individual contributor role requiring strong hands-on experience in Design Verification, with expertise at both block-level and top-level verification.

The ideal candidate will have extensive experience developing verification environments, debugging complex functional failures, running gate-level simulations, and driving coverage closure.

Key Responsibilities

• Own gate-level simulation testbench bring-up and debugging.
• Own power-aware verification using UPF.
• Collaborate with Physical Design teams to run and debug gate-level simulations.
• Work closely with SoC teams to debug functional failures during IP bring-up and feature execution.
• Create and maintain testbenches, verification environments, stimulus, and tests.
• Collaborate with RTL/design engineers to verify design features and resolve functional failures.
• Develop SystemVerilog assertions, checkers, covergroups, and constraints.
• Debug and root-cause functional failures from regression testing.
• Analyze code coverage and functional coverage and perform coverage gap analysis.
• Support silicon bring-up and root-cause hardware/functional failures.
• Contribute to verification strategy, execution, and overall coverage closure.

Required Qualifications

• Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of industry experience in Design Verification.
• Expert hands-on coding skills in testbench development, stimulus generation, checkers, and coverage closure.
• Strong experience with SystemVerilog and UVM or equivalent verification methodologies.
• 5+ years of hands-on experience with gate-level simulations.
• Strong knowledge of ARM protocols or equivalent, including:
• CHI
• AXI
• ACE-Lite
• APB
• Experience with Git version control.
• Strong scripting experience with Unix/Linux, Perl, and/or Python.
• Excellent written and verbal communication skills.