Senior IP/SoC Verification Engineer

Baya Systems; California (MO); On-site; USD 100,000 - 130,000; Full time

Job summary

A technology solutions firm is looking for a Senior Hardware Verification Engineer to develop test plans and implement verification strategies for complex IPs. The role involves significant collaboration with design teams to create testbenches and debug processes. Ideal candidates will have a BS/MS in Electrical Engineering or related field and over 8 years of relevant experience. Proficiency in Verilog and SystemVerilog is essential, along with the ability to work effectively on SOC-level verification projects.

Qualifications

• 8+ years of hands-on experience in block-level/IP-level/SOC-level verification.
• Proficiency in writing UVM/SystemVerilog code for test implementations.
• Familiarity with simulation and debug tools.

Responsibilities

• Collaborate with design and architecture teams to create test plans for configurable IPs.
• Implement the test plan and write UVM/SystemVerilog code.
• Define and implement configurable testbenches with software teams.
• Debug failures and close coverage in collaboration with design and DV engineers.

Skills

Verilog

SystemVerilog

Testbench development

Debugging

Education

BS/MS in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools

Job description

A technology solutions firm is looking for a Senior Hardware Verification Engineer to develop test plans and implement verification strategies for complex IPs. The role involves significant collaboration with design teams to create testbenches and debug processes. Ideal candidates will have a BS/MS in Electrical Engineering or related field and over 8 years of relevant experience. Proficiency in Verilog and SystemVerilog is essential, along with the ability to work effectively on SOC-level verification projects.