Hands-On Memory Subsystem Verification Engineer

Qualcomm; Santa Clara (CA); On-site; USD 153,000 - 230,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to drive memory subsystem verification, including memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic.

You will develop and execute verification strategies, build UVM-based testbenches, and write assertions, covering multiple modes and addressing complex verification challenges. The role requires strong Verilog/SystemVerilog/UVM skills, experience with constrained-random verification, and collaboration with RTL,

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, CS or related field.
• 3–10 years of ASIC/SoC verification experience.
• Hands-on with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Experience developing and debugging reusable UVM-based verification environments.
• Proficiency in building UVM components (sequences, drivers, monitors, scoreboards, agents, coverage).
• Experience with constrained-random and coverage-driven verification.
• Experience writing protocol, timing, and functional assertions.

Responsibilities

• Develop verification strategies, test plans, and coverage plans for complex RTL designs.
• Build and maintain reusable SystemVerilog/UVM environments and components.
• Create constrained-random, directed, and corner-case tests; include error-injection scenarios.
• Write SystemVerilog Assertions for protocol, interface, timing, and verification checks.
• Verify memory-controller, PHY-interface, and memory-subsystem functionality across modes.
• Analyze failures using waveform tools, logs, and transaction databases; drive root-cause analysis.
• Collaborate with RTL, architecture, modeling, and integration teams to resolve issues.
• Support regression, failure triage, and status reporting; drive closure of functional/code/coverage gaps.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Constrained-random verification

Formal verification

Education

Bachelor's degree

Master's degree

PhD

Tools

UPF

Verification IP

Job description

Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to drive memory subsystem verification, including memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic.

You will develop and execute verification strategies, build UVM-based testbenches, and write assertions, covering multiple modes and addressing complex verification challenges. The role requires strong Verilog/SystemVerilog/UVM skills, experience with constrained-random verification, and collaboration with RTL,