Lead VCS Verification Engineer – Deployments & Debugging

Synopsys, Inc.; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced verification engineer to lead VCS deployments at customer sites, working directly with design and verification teams to integrate the tool into existing flows and resolve adoption blockers.

You will diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure, while partnering with field engineers and R&D to translate pain points into product improvements.

Qualifications

• Bachelor's in Electronics or Computer Engineering with 5+ years of experience, or Master's with 3+ years, focused on digital design verification.
• Deep hands-on experience with simulation technologies, including VCS or equivalent commercial simulators, and strong understanding of event-driven simulation internals.
• Proficiency in SystemVerilog, UVM, SVA, and HDL languages like Verilog and VHDL, with the ability to read and debug complex testbenches and RTL.
• Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments.
• Strong scripting skills in Perl, TCL, Shell, and Make, with the ability to automate workflows and build tooling that improves engineer productivity.
• Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure.
• Experience with Synopsys tools like Verdi, exposure to low-power simulation, gate-level verification, and functional safety methodologies is a strong plus.

Responsibilities

• Lead VCS simulation deployments at customer sites, working directly with design and verification teams to integrate the tool into their existing flows and resolve adoption blockers.
• Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure.
• Partner with field application engineers and R&D to translate customer pain points into actionable product requirements and validate fixes in real customer environments.
• Drive competitive evaluations and benchmarking engagements, demonstrating VCS capabilities and building the technical case for adoption.
• Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows, improve simulation throughput, and reduce manual intervention.
• Interface with product validation and R&D teams to propose improvements in simulation accuracy, performance, and usability based on field feedback.
• Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.

Skills

SystemVerilog

UVM

SVA

Verilog

VHDL

Perl

TCL

Shell

Make

UNIX/Linux

Verdi

Education

Bachelor's in Electronics or Computer Engineering

Master's in Electronics or Computer Engineering

Tools

VCS

Verdi

Job description

Synopsys, Inc. is seeking an experienced verification engineer to lead VCS deployments at customer sites, working directly with design and verification teams to integrate the tool into existing flows and resolve adoption blockers.

You will diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure, while partnering with field engineers and R&D to translate pain points into product improvements.