Digital Verification Engineer — SystemVerilog/UVM Expert

Arrow Electronics; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Arrow Electronics seeks a Design Verification Engineer to join our Engineering & Design team in Austin, TX. You will develop and execute verification plans for complex digital designs and create SystemVerilog/UVM testbenches to ensure functional correctness and performance.

You will analyze coverage, debug failures, and collaborate with design, FPGA/ASIC, and validation teams to drive first-pass success and customer-focused innovation across diverse projects.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience in digital design verification and hardware verification methods.
• Strong knowledge of SystemVerilog and UVM.
• Ability to work across cross-functional teams and schedules.

Responsibilities

• Develop and execute verification plans for complex digital designs.
• Create and maintain SystemVerilog/UVM testbenches.
• Analyze coverage and debug failures to improve design quality.
• Collaborate with design, FPGA/ASIC, and validation teams.

Skills

SystemVerilog

UVM

Verification planning

Digital design verification

Debugging

Collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

UVM framework

Verilog/SystemVerilog tooling

Job description

Arrow Electronics seeks a Design Verification Engineer to join our Engineering & Design team in Austin, TX. You will develop and execute verification plans for complex digital designs and create SystemVerilog/UVM testbenches to ensure functional correctness and performance.

You will analyze coverage, debug failures, and collaborate with design, FPGA/ASIC, and validation teams to drive first-pass success and customer-focused innovation across diverse projects.