Lead ASIC Timing & Synthesis Engineer (SoC/IP)

Broadcom; Broomfield (CO); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

401K matching

ESPP

EAP

Paid holidays

Paid time off

Job summary

Broadcom is seeking a lead STA/ Synthesis engineer in Colorado to drive timing constraints, perform STA with PrimeTime/Tempus, and manage synthesis and audits for high-speed ASIC blocks. The role emphasizes timing signoff methodologies, QoR, and automation via Tcl/Perl.

Ideal candidates have 12+ years with either a Bachelor's or 10+ with a Masters, strong RTL/PMOS flow understanding, and proven ability to work independently in a fast-paced, cross-geographical environment.

Qualifications

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (Tcl, Perl).

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Perform static timing analysis (STA) using industry-standard tools (PrimeTime, Tempus).
• Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex blocks.
• Define and implement timing signoff methodologies, incl. process corners and derates.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis processes using Tcl or Perl.
• Provide guidance on clock tree synthesis and energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.
• Generate timing ECOs for timing closure.
• Drive timing closure for complex IP and ASIC blocks.

Skills

STA/ Synthesis

Timing closure

Scripting (Tcl/Perl)

Clock tree planning

STA tools (PrimeTime/Tempus)

RTL & ASIC flows

Teamwork

Education

Bachelor's degree in EE/CS

Master's degree

PhD (desirable)

Tools

PrimeTime

Tempus

DC-T

Genus

Fishtail

VCLP

Formality

Job description

Broadcom is seeking a lead STA/ Synthesis engineer in Colorado to drive timing constraints, perform STA with PrimeTime/Tempus, and manage synthesis and audits for high-speed ASIC blocks. The role emphasizes timing signoff methodologies, QoR, and automation via Tcl/Perl.

Ideal candidates have 12+ years with either a Bachelor's or 10+ with a Masters, strong RTL/PMOS flow understanding, and proven ability to work independently in a fast-paced, cross-geographical environment.