Lead IC Design Engineer — Timing & Synthesis

Broadcom; San Jose (CA); Presencial; USD 144.000 - 230.000; Tempo integral

Benefícios oferecidos por esta vaga

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

company paid holidays

paid sick leave and vacation time

Resumo da vaga

Broadcom is seeking a lead STA/Synthesis engineer to contribute to constraint development, validation, synthesis, and timing closure for mission critical IP and ASIC blocks. You will drive signoff methodologies, perform STA with PrimeTime/Tempus, and automate timing analyses across complex designs.

Ideal candidates have extensive experience with advanced nodes, RTL/SoC flows, and strong problem solving and communication skills.

Qualificações

• Bachelors plus extensive relevant experience across advanced tech nodes.
• Experience with RTL/ASIC design flows and timing signoff.
• Strong analytical and collaboration skills.

Responsabilidades

• Develop and validate timing constraints for complex SoCs.
• Perform STA using PrimeTime, Tempus, and other industry tools.
• Execute synthesis and audits (CDC, RDC, Low Power, equivalence).
• Define timing signoff methodologies including corners and derates.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis with Tcl or Perl scripting.
• Provide guidance on clock tree synthesis for energy efficiency.
• Drive timing closure for IP and ASIC blocks.

Conhecimentos

Lead STA

Synthesis

Constraint development

Tcl/Perl scripting

Timing closure

Problem solving

Communication & teamwork

Formação

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD (desirable)

Ferramentas

PrimeTime

Tempus

DC-T

Genus

Fishtail

VCLP

Formality

Descrição da vaga

Broadcom is seeking a lead STA/Synthesis engineer to contribute to constraint development, validation, synthesis, and timing closure for mission critical IP and ASIC blocks. You will drive signoff methodologies, perform STA with PrimeTime/Tempus, and automate timing analyses across complex designs.

Ideal candidates have extensive experience with advanced nodes, RTL/SoC flows, and strong problem solving and communication skills.