ASIC STA Engineer: Timing Closure & IP Delivery

Apple Inc.; Cupertino (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. in Cupertino seeks an ASIC STA Engineer to lead timing closure across complex SoCs. You will own timing closure for full chips and blocks, guiding timing verification and constraint generation across projects.

Work with multi-functional teams to resolve timing issues in deep sub-micron technologies. Strong digital design fundamentals and scripting in TCL/Perl are valuable, with Primetime familiarity a plus.

Qualifications

• Bachelor's degree with 3+ years in ASIC/STA timing.
• Strong fundamentals in digital design and timing concepts.
• Experience with timing tools such as Primetime is a plus.

Responsibilities

• Own full chip and block timing closure across projects.
• Develop timing verification methodologies and flows.
• Generation of block and full chip timing constraints.
• Collaborate with SOC teams to resolve complex timing issues.

Skills

Digital design

Self-starter

TCL scripting

Perl scripting

ASIC timing

STA tools

Synthesis flows

Constraint analysis

Cross-team comms

Education

Bachelor's degree + 3 years experience

Tools

Primetime

Galaxy Constraint Analyzer (GCA)

Job description

Apple Inc. in Cupertino seeks an ASIC STA Engineer to lead timing closure across complex SoCs. You will own timing closure for full chips and blocks, guiding timing verification and constraint generation across projects.

Work with multi-functional teams to resolve timing issues in deep sub-micron technologies. Strong digital design fundamentals and scripting in TCL/Perl are valuable, with Primetime familiarity a plus.