Lead STA & Synthesis Engineer - ASIC Timing & Signoff

Broadcom; Allentown (Lehigh County); Vor Ort; USD 144.000 - 230.000; Vollzeit

Zusammenfassung

Broadcom is seeking a lead STA/Synthesis engineer to contribute to constraint development, STA, synthesis, audits, and timing closure of IP and ASIC blocks in advanced nodes. You will implement timing signoff methodologies, automate analyses, and drive clock tree optimization across complex designs.

The role requires extensive experience in high-complexity silicon, RTL/SoC flows, and strong collaboration across teams. Competitive base salary and annual equity opportunities are provided.

Qualifikationen

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency in STA tools and scripting (Tcl, Perl).
• Proficiency with synthesis and audit tools for complex blocks.
• Understanding of RTL and place-and-route flows.
• Strong problem-solving and attention to detail.
• Excellent communication and teamwork abilities.
• Minimum Bachelor's + 12+ years or higher education equivalents

Aufgaben

• Develop and validate timing constraints for intricate SoC designs.
• Perform static timing analysis using industry tools (PrimeTime, Tempus).
• Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence).
• Define timing signoff methodologies including corners and derates.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis with Tcl or Perl scripts.
• Provide guidance on clock tree synthesis for energy efficiency.
• Ensure compliance with timing signoff checklists.
• Generate timing ECOs and drive timing closure for IP/ASIC blocks

Kenntnisse

STA/Timing analysis

Clock tree planning

RTL/Design experience

Scripting (Tcl, Perl)

Teamwork & communication

Ausbildung

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD preferred

Tools

PrimeTime

TCM

Tempus

DC-T

Genus

Fishtail

VCLP

Formality

Jobbeschreibung

Broadcom is seeking a lead STA/Synthesis engineer to contribute to constraint development, STA, synthesis, audits, and timing closure of IP and ASIC blocks in advanced nodes. You will implement timing signoff methodologies, automate analyses, and drive clock tree optimization across complex designs.

The role requires extensive experience in high-complexity silicon, RTL/SoC flows, and strong collaboration across teams. Competitive base salary and annual equity opportunities are provided.