Lead ASIC Timing & STA Automation Engineer

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 170,000 - 210,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose, CA, is seeking an ASIC Design STA engineer to help develop timing constraints for large SoCs with many clock domains.

You will work across RTL, synthesis, and place-and-route, applying SDC expertise and TCL scripting to automate workflows and improve QoR. The role requires hands-on experience with Design Compiler and PrimeTime, strong communication, and the ability to collaborate with CAD teams on pre-production flows.

Qualifications

• Bachelor's or Master's degree in computer engineering or electrical engineering.
• Experience with EDA toolchains and RTL-to-Gates flow.
• Strong communication and collaborative skills.

Responsibilities

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
• Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.
• Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks.
• Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.
• Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)

Skills

SDC expertise

Tcl scripting

EDA tools proficiency

RTL quality metrics automation

Front-end / RTL & back-end timing

Timing constraints development

Education

Bachelor's or Master's degree in Computer or Electrical Engineering

Tools

Synopsys Design Compiler

Primetime

Spyglass

Fishtail

Linux TCL scripting (DC/PT)

Job description

Advanced Micro Devices, Inc. in San Jose, CA, is seeking an ASIC Design STA engineer to help develop timing constraints for large SoCs with many clock domains.

You will work across RTL, synthesis, and place-and-route, applying SDC expertise and TCL scripting to automate workflows and improve QoR. The role requires hands-on experience with Design Compiler and PrimeTime, strong communication, and the ability to collaborate with CAD teams on pre-production flows.