ASIC Timing & Sign-off Engineer (STA)

Apple Inc.; San Diego (CA); On-site; USD 122,700 - 214,300; Full time

Job summary

Apple Inc. is seeking an ASIC STA Engineer to drive timing sign‑off and flow development across the SoC. You will own IP and block level timing constraints from synthesis to sign‑off, interfacing with RTL, CAD, and Physical Design to achieve timely closure.

The role emphasizes expertise in timing constraints, attention to variations, and strong collaboration across diverse groups at Apple.

Qualifications

• Bachelors of Science in Electrical Engineering.
• Experience with ASIC timing constraints and timing closure preferred.

Responsibilities

• Perform timing sign‑off and develop sign‑off flow.
• Own IP and block level timing constraints for Synthesis to sign‑off.
• Collaborate with RTL to understand design intent and clock structure.
• Work with CAD to develop timing flow and constraints.
• Coordinate with Physical Design to close timing.
• Propose ideas to verify timing constraints and improve flows.
• Innovate timing constraints and flows to enable timing closure.

Skills

ASIC timing

Timing closure

Primetime

Tcl scripting

Perl scripting

Synthesis

DFT

Clock structure

Communication

Education

Bachelor's degree in Electrical Engineering

Job description

Apple Inc. is seeking an ASIC STA Engineer to drive timing sign‑off and flow development across the SoC. You will own IP and block level timing constraints from synthesis to sign‑off, interfacing with RTL, CAD, and Physical Design to achieve timely closure.

The role emphasizes expertise in timing constraints, attention to variations, and strong collaboration across diverse groups at Apple.