Lead Silicon Verification Engineer - Networking IP

Anysilicon; Santa Clara (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices, Inc. seeks an experienced verification lead in Santa Clara to drive IP/SoC verification for networking solutions.

You will define strategies, build scalable UVM environments, and guide cross-functional teams in high-speed Ethernet, PCIe, and DMA verification. We expect expert SystemVerilog/UVM skills, strong debugging ability, and a track record of delivering signed-off verification for complex IP.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field; Master’s preferred.
• Expert-level SystemVerilog and UVM knowledge.
• Hands-on experience with SystemVerilog simulators and waveform debuggers.
• Experience verifying complex IP/subsystems with test plans and coverage.
• Strong debug skills across architecture, RTL and testbench layers.

Responsibilities

• Lead verification of complex networking IP, subsystems, and SoCs.
• Define verification strategy and scalable environments for high-speed Ethernet, PCIe, DMA, etc.
• Drive functional and performance verification to signoff on next-gen networking products.
• Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
• Create test plans, feature mappings, and coverage strategies for networking/IP.
• Verify networking functions including packet processing, switch fabrics, and traffic management.
• Own execution of verification plans and debug architectural, functional, and performance issues.
• Collaborate with cross-functional teams and participate in design reviews.
• Mentor junior engineers and provide technical leadership within the verification team.

Skills

SystemVerilog

UVM

Python scripting

Ethernet/PCIe knowledge

Debugging

Education

Bachelor’s Degree in Electrical/Computer Engineering or related field

Master’s degree preferred

Tools

SystemVerilog simulators

Waveform debuggers

Job description

Advanced Micro Devices, Inc. seeks an experienced verification lead in Santa Clara to drive IP/SoC verification for networking solutions.

You will define strategies, build scalable UVM environments, and guide cross-functional teams in high-speed Ethernet, PCIe, and DMA verification. We expect expert SystemVerilog/UVM skills, strong debugging ability, and a track record of delivering signed-off verification for complex IP.