Networking Silicon DV Engineer (MTS)

AMD; Santa Clara (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

AMD’s Network Technologies Solutions Group (NTSG) is seeking a hands-on MTS Design Verification Engineer to lead verification of complex networking IP, subsystems, and SoCs. You will define verification strategy, develop scalable environments, and drive functional and performance verification to signoff, spanning Ethernet, PCIe, DMA, and traffic management.

You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking

Qualifications

• Expert-level knowledge of SystemVerilog and UVM.
• Hands-on experience with SystemVerilog simulators (VCS) and waveform debuggers (Verdi/DVE).
• Proven verification of complex IP/subsystems with test plans, coverage, and constrained-random methodologies.
• Strong debugging across architecture, RTL, and testbench layers.
• Experience with PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components.

Responsibilities

• Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.
• Develop high-quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
• Verify networking and data-path functions including Ethernet, PCIe, DMA, packet processing, switch fabrics, and traffic management.
• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
• Optimize simulations, coverage closure, and verification sign-off methodology.
• Use tools and methodologies (VCS, Verdi/DVE, coverage tools) and contribute to automation (Python/Tcl/Make).
• Collaborate with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.

Skills

SystemVerilog

UVM

Debugging

Testbench

Coverage

Python scripting

Education

Bachelor’s Degree in Electrical/Computer Engineering

Tools

VCS

Verdi/DVE

Python scripting

Waveform analysis

Job description

AMD’s Network Technologies Solutions Group (NTSG) is seeking a hands-on MTS Design Verification Engineer to lead verification of complex networking IP, subsystems, and SoCs. You will define verification strategy, develop scalable environments, and drive functional and performance verification to signoff, spanning Ethernet, PCIe, DMA, and traffic management.

You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking