Lead SerDes Design Architect for High-Speed AI Interconnect

Celero Communications, Inc.; United States; Remote; USD 180,000 - 260,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architecture and implementation of next-generation SerDes for AI-ready interconnects.

You will drive system-level modeling, develop high-speed analog/mixed-signal blocks, and guide tape-out and production readiness in a renowned lab environment. The role requires 10+ years in SerDes design, deep knowledge of 16nm–2nm nodes, and a proven track record of delivering IP integrated into SOCs.

Qualifications

• Master’s or PhD in Electrical Engineering or related field.
• 10+ years of relevant SerDes design experience.
• Proven track record from design to tape-out in high-speed SerDes.
• Experience with lab bring-up, characterization and debugging for production.
• Experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm).

Responsibilities

• Define architecture, specifications, and topologies for next-generation SerDes.
• Oversee system-level modelling with MATLAB, SystemVerilog, or Verilog-A.
• Design high-performance analog/mixed-signal circuits in advanced nodes.
• Develop and oversee RX/TX equalization, PLLs, DLLs, and TDCs.
• Implement digitally assisted analog circuits and adaptive loops.
• Oversee physical layout to minimize parasitics and variation impacts.
• Lead lab validation, debugging, and characterization of SerDes IPs.
• Correlate silicon measurements with simulations and optimize performance.

Skills

High-speed SerDes design

Tape-out experience

Lab bring-up & debugging

Cross-functional teamwork

Communication & documentation

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

MATLAB

SystemVerilog

Verilog-A

Job description

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architecture and implementation of next-generation SerDes for AI-ready interconnects.

You will drive system-level modeling, develop high-speed analog/mixed-signal blocks, and guide tape-out and production readiness in a renowned lab environment. The role requires 10+ years in SerDes design, deep knowledge of 16nm–2nm nodes, and a proven track record of delivering IP integrated into SOCs.