Senior SerDes DSP Design Engineer for AI Networking

ArcTern Ventures; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

HYPERLUME in San Jose, CA is seeking a Principal Design Engineer to lead RTL architecture, design, implementation and verification of advanced SerDes PHY DSP blocks for next‑generation networking and AI products.

In this role you will collaborate with cross‑functional teams to define specifications and deliver high‑performance silicon, with a focus on reliability, scalability and power efficiency.

Qualifications

• Experience with RTL architecture, design and verification.

Responsibilities

• Lead RTL architecture and SerDes PHY DSP block design, implementation and verification.
• Collaborate with hardware and software teams to define specs for networking and AI products.

Job description

HYPERLUME in San Jose, CA is seeking a Principal Design Engineer to lead RTL architecture, design, implementation and verification of advanced SerDes PHY DSP blocks for next‑generation networking and AI products.

In this role you will collaborate with cross‑functional teams to define specifications and deliver high‑performance silicon, with a focus on reliability, scalability and power efficiency.