Principal SerDes Design Engineer

Celero Communications, Inc.; United States; À distance; USD 180 000 - 260 000; Plein temps

Résumé du poste

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architecture and implementation of next-generation SerDes for AI-ready interconnects.

You will drive system-level modeling, develop high-speed analog/mixed-signal blocks, and guide tape-out and production readiness in a renowned lab environment. The role requires 10+ years in SerDes design, deep knowledge of 16nm–2nm nodes, and a proven track record of delivering IP integrated into SOCs.

Qualifications

• Master’s or PhD in Electrical Engineering or related field.
• 10+ years of relevant SerDes design experience.
• Proven track record from design to tape-out in high-speed SerDes.
• Experience with lab bring-up, characterization and debugging for production.
• Experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm).

Responsabilités

• Define architecture, specifications, and topologies for next-generation SerDes.
• Oversee system-level modelling with MATLAB, SystemVerilog, or Verilog-A.
• Design high-performance analog/mixed-signal circuits in advanced nodes.
• Develop and oversee RX/TX equalization, PLLs, DLLs, and TDCs.
• Implement digitally assisted analog circuits and adaptive loops.
• Oversee physical layout to minimize parasitics and variation impacts.
• Lead lab validation, debugging, and characterization of SerDes IPs.
• Correlate silicon measurements with simulations and optimize performance.

Connaissances

High-speed SerDes design

Tape-out experience

Lab bring-up & debugging

Cross-functional teamwork

Communication & documentation

Formation

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Outils

MATLAB

SystemVerilog

Verilog-A

Description du poste

Principal SerDes Design Engineer

About the job

We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do

• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills