SerDes Design & Validation Engineer — High‑Speed IP Leader

Apple Inc.; Cupertino (CA); Hybrid; USD 129,000 - 225,000; Full time

Benefits offered by this job

Stock options

Relocation assistance

Educational reimbursement

Job summary

Apple Inc. is seeking a SerDes Design and Validation Engineer in Cupertino to lead system validation of mixed-signal SerDes IP. You will design, integrate and validate high-speed analog/mixed-signal blocks, develop test plans, and drive production test readiness with design teams.

A strong background in SerDes, DFT, and AMS IC development is required, with a track record of lab testing and data analysis. The role emphasizes collaboration, innovation, and driving silicon success across

Qualifications

• Minimum: a bachelor’s degree.
• Experience with high-speed SerDes, analog/digital mixed-signal blocks and testability required or strongly preferred.
• Experience in system validation, lab testing and ATE/system validation is highly desirable.

Responsibilities

• Ownership of SerDes system bring-up, validation and debug.
• Collaborate with design teams to define DFT needs and testability improvements.
• Engage in mixed-signal verification to understand SerDes operation and interaction with higher level control logic.

Skills

High-speed SerDes

Analog mixed-signal design

DFT/test automation

AMS IC development

Scripting

Lab testing

AI/ML for silicon

System validation

Education

Bachelor's degree

Tools

Python scripting

AMS IC design tools

Job description

Apple Inc. is seeking a SerDes Design and Validation Engineer in Cupertino to lead system validation of mixed-signal SerDes IP. You will design, integrate and validate high-speed analog/mixed-signal blocks, develop test plans, and drive production test readiness with design teams.

A strong background in SerDes, DFT, and AMS IC development is required, with a track record of lab testing and data analysis. The role emphasizes collaboration, innovation, and driving silicon success across